1. Field of the Invention
The present invention relates to a semiconductor device which is optimal to provide a large wafer area and a large number of functions formed on the wafer or less number of parts to be fabricated, and a method for fabricating it. The semiconductor device according to the present invention is suitable to realize a large capacity and high performance.
2. Description of the Related Art
Heretofore, a semiconductor device has been required to have plural functions such as functions of arithmetic, storage and input/output on its monolithic chip. But an increase in the chip area leads to a considerable reduction in the fabrication yield so that such requirement has been dealt with by curtailing each function and reducing the area occupied by each function.
Thus, the semiconductor device has been constructed with each function made lower than the case where a single chip has a single function. Its one example is HD401220 eight-bit single chip microcomputer described in HITACHI MICROCOMPUTER GENERAL USER'S GUIDE February 1991 page 121.
This microcomputer chip has many functions including a 2048-byte ROM, 32-byte EEPROM, timer, D/A converter and I/O port. The performance of each function is inferior to that in the system including HD64180 eight-bit microcomputer and 4MDRAM named HM514102. The technology of combining plural chips to form a single semiconductor device is disclosed in JP-A-2-184063.
The former technology, in which each function is made lower than in the case of the single-chip single-function, is not suitable to the case where upgraded functions are required.
The latter technology, in which the gaps necessarily generated between chips are filled with resin, cannot be applicable to a high temperature process. The reason why the gaps are generated is that the chips etched by isotropic etching or insufficient anisotropic etching are combined.
Conventional defect relief technology for LSI with the scale of a semiconductor substrate is disclosed in e.g. (1) "NIKKEI MICRODEVICE" April 1986, pages 45-46 issued Apr. 1, 1986 by Nikkei McGraw-Hill Inc., and (2) JP-A-62-147746.
The reference (1) makes an explanation of the defect relief technology for the integrated circuit with the scale of a substrate. Its summary is as follows. First, poor device areas of device areas on the substrate are removed, and at the removed areas planar square holes each penetrating from the principal surface of the substrate to the back surface thereof are formed. Secondly, the substrate, under the state where the principal surface is directed downward, is placed on a prescribed pedestal. Subsequently, defect-free semiconductor elements chips, under the state where their principal surface is directed downward, are inserted or mounted in the holes. The size of the defect-free element chips inserted in the holes is e.g. 4.98 mm square or so. Thereafter, the gaps between the defect-free element chips and the substrate are filled with resin such as epoxy resin. Finally, the substrate is turned over and wirings are made between the pads of the defect-free element chips and those for the defect-free areas on the substrate, thus completing the integrated circuit.
The reference (2) also describes a defect relief technique for integrated circuits. Like the reference (1), in this technique also, defective element areas on a substrate are removed and defect-free element chips are inserted in the removed areas; thereafter wirings are made between the element chips to complete an integrated circuit.
In recent years, the semiconductor devices have been advanced to provide large capacity and upgraded function, and also the element chips included in the device have been advanced to provide upgraded function and large size. But if the element chips are made large-sized, the number of element areas which can be formed on the substrate will be reduced. In addition, if the element chips are made large-sized and also highly integrated, the defect production rate will be increased owing to alien substances. As a result, the number of defect-free element chips which can be acquired from a single substrate will be greatly decreased.
Thus, it is expected that realizing the large capacity and upgraded function of the semiconductor device makes it very difficult to assure the element production yield profitable in cost. The method which may reduce the number of defect-free element chips which can be acquired from a single semiconductor substrate to one or less cannot be used for the production of the semiconductor device. From such a standpoint, as a future trend of the semiconductor devices, an important problem to be solved is to provide a method of fabricating a semiconductor device with high production yield or realizing defect relief with high reliability.
Further, in recent years, development and fabrication of custom products for semiconductor devices have been advanced. The custom products are fabricated in accordance with the specification requested by a user by the number required by him. Thus, the number of the kinds of products is increased whereas the number of products for each kind is not increased. As a result, reduction in the production cost for the products due to mass-production cannot be expected. The cost of the products will greatly depend on the element production yield. In order to assure the element yield profitable in cost, the defect relief technique with high reliability is required as in the above case.
In the conventional techniques disclosed in the above references (1) and (2), defective element chips cannot be easily removed and defect-free element chips cannot be precisely positioned when they are to be mounted on a substrate so that the wiring method of connecting the elements with the substrate is problematic. The conventional techniques, as they are, cannot be adopted as relief technique for elements.